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IDT59910A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LOW SKEW PLL CLOCK DRIVER TURBOCLOCKTM JR.
FEATURES:
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IDT59910A
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Eight zero delay outputs Selectable positive or negative edge synchronization Synchronous output enable Output frequency: 15MHz to 100MHz TTL outputs 3 skew grades: IDT59910A-2: tSKEW0<250ps IDT59910A-5: tSKEW0<500ps IDT59910A-7: tSKEW0<750ps 3-level inputs for PLL range control PLL bypass for DC testing External feedback, internal loop filter 46mA IOL high drive outputs Low Jitter: <200ps peak-to-peak Outputs drive 50 terminated lines Pin-compatible with Cypress CY7B9910 Available in SOIC package
DESCRIPTION:
The IDT59910A is a high fanout phase lock loop clock driver intended for high performance computing and data-communications applications. The IDT59910A has eight zero delay TTL outputs. The IDT59910A maintains Cypress CY7B9910 compatibility while providing two additional features: Synchronous Output Enable (GND/sOE), and Positive/Negative Edge Synchronization (VCCQ/PE). When the GND/ sOE pin is held low, all the outputs are synchronously enabled (CY7B9910 compatibility). However, if GND/sOE is held high, all the outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the VCCQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input (CY7B9910 compatibility). When VCCQ/PE is held low, all the outputs are synchronized with the negative edge of REF. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
FUNCTIONAL BLOCK DIAGRAM
VCCQ/PE GND/sOE Q0 Q1
Q2 Q3 PLL REF Q4 Q5 FS Q6 Q7
FB
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
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c 2001 Integrated Device Technology, Inc.
SEPTEMBER 2001
DSC 5845/1
IDT59910A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
REF VCCQ FS NC VCCQ/PE VCCN Q0 Q1 GND Q2 Q3 VCCN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GND TEST NC GND/sOE VCCN Q7 Q6 GND Q5 Q4 VCCN FB
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VI TSTG Description Supply Voltage to Ground DC Input Voltage Maximum Power Dissipation (TA = 85C) Storage Temperature Max -0.5 to +7 -0.5 to +7 530 -65 to +150 Unit V V mW C
NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
Parameter CIN Description Input Capacitance Typ. 5 Max. 7 Unit pF
SOIC TOP VIEW
NOTE: 1. Capacitance applies to all inputs except TEST and FS. It is characterized but not production tested.
PIN DESCRIPTION
Pin Name REF FB TEST (1) GND/ sOE(1) VCCQ/PE FS(2) Type IN IN IN IN IN IN Description Reference Clock Input Feedback Input When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as the feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation. Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. Frequency range select. 3 level input. FS = GND: 15 to 35MHz FS = MID (or open): 25 to 60MHz FS = VCC: 40 to 100MHz Q0 - Q7 VCCN VCCQ GND OUT PWR PWR PWR Eight clock output Power supply for output buffers Power supply for phase locked loop and other internal circuitry Ground
NOTES: 1. When TEST = MID and GND/sOE = HIGH, PLL remains active. 2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional lock time before all data sheet limits are achieved.
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IDT59910A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING RANGE
IDT59910A-5, -7 (Industrial) Symbol VCC TA Description Power Supply Voltage Ambient Operating Temperature Min. 4.5 -40 Max. 5.5 +85 IDT59910A-2 (Commercial) Min. 4.75 0 Max. 5.25 +70 Unit V C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol VIH VIL VIHH VIMM VILL IIN Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Voltage(1) Input MID Voltage
(1)
Conditions Guaranteed Logic HIGH (REF, FB Inputs Only) Guaranteed Logic LOW (REF, FB Inputs Only) 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VIN = VCC or GND
VCC = Max.
Min. 2 --
VCC-1 VCC/2-0.5
Max. -- 0.8 --
VCC/2+0.5
Unit V V V V V A
Input LOW Voltage(1) Input Leakage Current (REF, FB Inputs Only)
-- -- HIGH Level MID Level LOW Level -- -- -- -- -- 2.4 -- -- --
1 5 200 50 200 100 100 -- -- 0.45
VIN = VCC I3 IPU IPD VOH VOL IOS 3-Level Input DC Current (TEST, FS) Input Pull-Up Current (VCCQ/PE) Input Pull-Down Current (GND/sOE) Output HIGH Voltage Output LOW Voltage Output Short Circuit Current
(2)
VIN = VCC/2 VIN = GND
VCC = Max., VIN = GND VCC = Max., VIN = VCC
A A A V V mA
-16mA VCC = Min., IOH = -40mA
VCC = Min., IOH = VCC = Min., IOL = 46mA VCC = Max., VO = GND
-250
NOTES: 1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 2. This is to be measured at 25C with 10:1 duty cycle, one output at a time, and one second maximum.
POWER SUPPLY CHARACTERISTICS
Symbol ICCQ ICC ICCD ITOT Parameter Quiescent Power Supply Current Power Supply Current per Input HIGH Dynamic Power Supply Current per Output Total Power Supply Current Test Conditions(1) VCC = Max., TEST = MID, REF = LOW, GND/sOE = LOW, All outputs unloaded VCC = Max., VIN = 3.4V VCC = Max., CL = 0pF VCC = 5V, FREF = 25MHz, CL = 240pF(1) VCC = 5V, FREF = 33MHz, CL = 240pF(1) VCC = 5V, FREF = 66MHz, CL =
NOTE: 1. For eight outputs, each loaded with 30pF.
Typ.(2) 10 0.4 100 53 63 117
Max. 40 1.5 160 -- -- --
Unit mA mA A/MHz mA
240pF(1)
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IDT59910A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Symbol tR, tF tPWC DH REF Description (1) Maximum input rise and fall times, 0.8V to 2V Input clock pulse, HIGH or LOW Input duty cycle Reference clock input Min. -- 3 10 15 Max. 10 -- 90 100 Unit ns/V ns % MHz
NOTE: 1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT59910A-2 Symbol Parameter FS = LOW FREF tRPWH tRPWL tSKEW0 tDEV tPD tODCV tORISE tOFALL tLOCK tJR REF Frequency Range REF Pulse Width HIGH
(1,8)
IDT59910A-5 Max. 35 60 100 -- -- 0.25 0.75 0.25 1.2 1.2 1.2 0.5 25 200 Min. 15 25 40 3 3 -- -- Typ. -- -- -- -- -- 0.25 -- 0 0 1 1 -- -- -- Max. 35 60 100 -- -- 0.5 1.25 0.5 1.2 1.5 1.5 0.5 25 200 Min. 15 25 40 3 3 -- --
IDT59910A-7 Typ. -- -- -- -- -- 0.3 -- 0 0 1.5 1.5 -- -- -- Max. 35 60 100 -- -- 0.75 1.65 0.7 1.2 2.5 2.5 0.5 25 200 ns ns ns ns ns ns ns ns ms ps MHz Unit
Min. 15 25 40 3 3
(1,3,4)
Typ. -- -- -- -- -- 0.1 -- 0 0 1 1 -- -- --
FS = MED FS = HIGH
REF Pulse Width LOW(1,8) Zero Output Skew (All Outputs) Device-to-Device Skew(1,2,5) REF Input to FB Propagation Delay(1,7) Output Duty Cycle Variation from 50% Output Rise Time(1) Output Fall Time
(1) (1)
-- --
-0.25 -1.2
0.15 0.15 --
-0.5 -1.2
0.15 0.15 -- -- --
-0.7 -1.2
0.15 0.15 -- -- --
PLL Lock Time(1,6) Cycle-to-Cycle Output Jitter(1) RMS Peak-to-Peak
-- --
NOTES: 1. All timing and jitter tolerances apply for FNOM > 25MHz. 2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load. 3. tSKEW is the skew between all outlets. See AC TEST LOADS. 4. For IDT59910A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.35ns Max. 5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) 6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 7. tPD is measured with REF input rise and fall times (from 0.8V to 2V ) of 1ns. 8. Refer to INPUT TIMING REQUIREMENTS for more detail.
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IDT59910A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TEST LOADS AND WAVEFORMS
VCC
3.0V 2.0V Vth =1.5V
1ns
1ns
130 Output
0.8V 0V
TTL Input Test Waveform
91 CL
CL = 50pF (CL = 30pF for -2 and -5 devices)
tOR ISE
tOFAL L
Test Load
2.0V
0.8V
TTL Output Waveform
AC TIMING DIAGRAM
tREF tRPW H REF tRPWL
tPD
tODCV
tODCV
FB
tJR
Q tSKEW tSKEW
OTHER Q
NOTES: Skew: tSKEW: tDEV: tODCV: tLOCK:
The time between the earliest and the latest output transition among all outputs when all are loaded with 50pF (30pF for -2 and -5) and terminated with 50 to 2.06V. The skew between all outputs. The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) The deviation of the output from a 50% duty cycle. The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
tORISE and tOFALL are measured between 0.8V and 2V.
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IDT59910A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Process
Blank I SO
Commercial (0C to +70C) Industrial (-40C to +85C) Small Outline IC (300-mil)
59910A-2 Low Skew PLL Clock Driver TurboClock Jr. 59910A-5 59910A-7
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6
for Tech Support: logichelp@idt.com (408) 654-6459

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